Job Description Summary:
\nDraper’s Digital Design Team is seeking a motivated and experienced Senior UVM Digital Verification Engineer to tackle novel verification challenges in FPGAs and ASICs. In this role, you will apply modern verification strategies to complex digital and mixed-signal designs in the areas of embedded security, cryptography, signal and image processing, navigation and communications.
\n \nJob Description:
\n Duties/Responsibilities
• Performs analysis approaches for a particular problem and independently execute assignments.
• Independently execute system engineering lifecycle assignments; concept and architecture design, integration, testing and operation.
• Drive solutions to complex problems with limited direction – contribute to task planning and test development, propose ways forward, and adapt appropriately to changes in program requirements
• Demonstrated ability to lead small teams (fewer than five people). Seeks to align team towards program goals and builds trust within the team.
• Able to provide insight and suggest design modifications based on analysis outcomes, and to apply analysis techniques across a range of technical challenges.
• Identify program/system-level technical risks and develop and execute mitigation strategies for them.
• Actively mentor less experienced engineers and provide thoughtful, constructive feedback.
• Work in a collaborative multidisciplinary environment including stakeholders and external partners.
• Contribute to translation of requirements into technical and architectural decisions.
Additional Job Description:
\n \nYou will develop verification approaches, author and execute verification plans, and use formal analysis tools. You will work in multi-disciplinary teams with opportunities to learn, grow and contribute to a variety of projects. Join us as we develop the next generation of digital and embedded hardware platforms.
\nApplicants selected for this position will have or be able to obtain and maintain a government security clearance.
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